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164 lines
6.0 KiB
C
164 lines
6.0 KiB
C
#ifndef PCI_H
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#define PCI_H
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/*
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** Support for NE2000 PCI clones added David Monro June 1997
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** Generalised for other PCI NICs by Ken Yap July 1997
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**
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** Most of this is taken from:
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**
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** /usr/src/linux/drivers/pci/pci.c
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** /usr/src/linux/include/linux/pci.h
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** /usr/src/linux/arch/i386/bios32.c
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** /usr/src/linux/include/linux/bios32.h
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** /usr/src/linux/drivers/net/ne.c
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*/
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2, or (at
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* your option) any later version.
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*/
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
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#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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#define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
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#define PCIBIOS_PCI_BIOS_PRESENT 0xb101
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#define PCIBIOS_FIND_PCI_DEVICE 0xb102
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#define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
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#define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
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#define PCIBIOS_READ_CONFIG_BYTE 0xb108
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#define PCIBIOS_READ_CONFIG_WORD 0xb109
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#define PCIBIOS_READ_CONFIG_DWORD 0xb10a
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#define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
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#define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
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#define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_CLASS_CODE 0x0b /* 8 bits */
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#define PCI_SUBCLASS_CODE 0x0a /* 8 bits */
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#define PCI_HEADER_TYPE 0x0e /* 8 bits */
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#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */
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#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */
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#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
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#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
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#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
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#ifndef PCI_BASE_ADDRESS_IO_MASK
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#define PCI_BASE_ADDRESS_IO_MASK (~0x03)
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#endif
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#define PCI_BASE_ADDRESS_SPACE_IO 0x01
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#define PCI_ROM_ADDRESS 0x30 /* 32 bits */
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#define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM,
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bits 31..11 are address,
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10..2 are reserved */
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#define PCI_FUNC(devfn) ((devfn) & 0x07)
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#define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
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/* PCI signature: "PCI " */
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#define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
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/* PCI service signature: "$PCI" */
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#define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
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union bios32 {
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struct {
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unsigned long signature; /* _32_ */
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unsigned long entry; /* 32 bit physical address */
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unsigned char revision; /* Revision level, 0 */
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unsigned char length; /* Length in paragraphs should be 01 */
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unsigned char checksum; /* All bytes must add up to zero */
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unsigned char reserved[5]; /* Must be zero */
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} fields;
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char chars[16];
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};
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#define KERN_CODE_SEG 0x8 /* This _MUST_ match start.S */
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/* Stuff for asm */
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#define save_flags(x) \
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__asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */ :"memory")
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#define cli() __asm__ __volatile__ ("cli": : :"memory")
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#define restore_flags(x) \
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__asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory")
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#define PCI_VENDOR_ID_ADMTEK 0x1317
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#define PCI_DEVICE_ID_ADMTEK_0985 0x0985
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#define PCI_VENDOR_ID_REALTEK 0x10ec
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#define PCI_DEVICE_ID_REALTEK_8029 0x8029
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#define PCI_DEVICE_ID_REALTEK_8139 0x8139
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#define PCI_VENDOR_ID_WINBOND2 0x1050
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#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940
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#define PCI_VENDOR_ID_COMPEX 0x11f6
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#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401
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#define PCI_VENDOR_ID_KTI 0x8e2e
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#define PCI_DEVICE_ID_KTI_ET32P2 0x3000
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#define PCI_VENDOR_ID_NETVIN 0x4a14
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#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000
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#define PCI_VENDOR_ID_3COM 0x10b7
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#define PCI_DEVICE_ID_3COM_3C590 0x5900
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#define PCI_DEVICE_ID_3COM_3C595 0x5950
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#define PCI_DEVICE_ID_3COM_3C595_1 0x5951
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#define PCI_DEVICE_ID_3COM_3C595_2 0x5952
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#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000
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#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001
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#define PCI_DEVICE_ID_3COM_3C905TX 0x9050
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#define PCI_DEVICE_ID_3COM_3C905T4 0x9051
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#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055
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#define PCI_DEVICE_ID_3COM_3C905C_TXM 0x9200
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_82557 0x1229
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#define PCI_VENDOR_ID_AMD 0x1022
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#define PCI_DEVICE_ID_AMD_LANCE 0x2000
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#define PCI_VENDOR_ID_SMC_1211 0x1113
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#define PCI_DEVICE_ID_SMC_1211 0x1211
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#define PCI_VENDOR_ID_DEC 0x1011
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#define PCI_DEVICE_ID_DEC_TULIP 0x0002
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#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009
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#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014
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#define PCI_DEVICE_ID_DEC_21142 0x0019
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#define PCI_VENDOR_ID_SMC 0x10B8
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#ifndef PCI_DEVICE_ID_SMC_EPIC100
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# define PCI_DEVICE_ID_SMC_EPIC100 0x0005
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#endif
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#define PCI_VENDOR_ID_MACRONIX 0x10d9
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#define PCI_DEVICE_ID_MX987x5 0x0531
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#define PCI_VENDOR_ID_LINKSYS 0x11AD
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#define PCI_DEVICE_ID_LC82C115 0xC115
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#define PCI_VENDOR_ID_VIATEC 0x1106
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#define PCI_DEVICE_ID_VIA_RHINE_I 0x3043
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#define PCI_DEVICE_ID_VIA_86C100A 0x6100
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#define PCI_VENDOR_ID_DAVICOM 0x1282
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#define PCI_DEVICE_ID_DM9102 0x9102
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struct pci_device {
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unsigned short vendor, dev_id;
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const char *name;
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unsigned int membase;
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unsigned short ioaddr;
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unsigned short devfn;
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};
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extern void eth_pci_init(struct pci_device *);
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extern int pcibios_read_config_byte(unsigned char bus, unsigned char device_fn, unsigned char where, unsigned char *value);
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extern int pcibios_write_config_byte (unsigned char bus, unsigned char device_fn, unsigned char where, unsigned char value);
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extern int pcibios_read_config_word(unsigned char bus, unsigned char device_fn, unsigned char where, unsigned short *value);
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extern int pcibios_write_config_word (unsigned char bus, unsigned char device_fn, unsigned char where, unsigned short value);
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extern int pcibios_write_config_dword(unsigned char bus,
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unsigned char device_fn, unsigned char where, unsigned int value);
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#endif /* PCI_H */
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