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/*
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* 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
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* by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith,
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* Steve.Smith@Juno.Com
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*
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* This program Copyright (C) 1999 LightSys Technology Services, Inc.
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* Portions Copyright (C) 1999 Steve Smith
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*
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* This program may be re-distributed in source or binary form, modified,
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* sold, or copied for any purpose, provided that the above copyright message
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* and this text are included with all source copies or derivative works, and
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* provided that the above copyright message and this text are included in the
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* documentation of any binary-only distributions. This program is distributed
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* WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
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* PURPOSE or MERCHANTABILITY. Please read the associated documentation
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* "3c90x.txt" before compiling and using this driver.
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*
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* --------
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*
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* Program written with the assistance of the 3com documentation for
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* the 3c905B-TX card, as well as with some assistance from the 3c59x
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* driver Donald Becker wrote for the Linux kernel, and with some assistance
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* from the remainder of the Etherboot distribution.
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*
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* REVISION HISTORY:
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*
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* v0.10 1-26-1998 GRB Initial implementation.
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* v0.90 1-27-1998 GRB System works.
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* v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
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* v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
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* Re-wrote poll and transmit for
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* better error recovery and heavy
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* network traffic operation
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*
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*/
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#include "etherboot.h"
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#include "nic.h"
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#ifndef __FreeBSD__
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#include <linux/pci.h>
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#endif
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#define TIME_OUT 60000
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#define XCVR_MAGIC (0x5A00)
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/** any single transmission fails after 16 collisions or other errors
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** this is the number of times to retry the transmission -- this should
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** be plenty
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**/
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#define XMIT_RETRIES 250
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#undef virt_to_bus
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#define virt_to_bus(x) ((unsigned long)x)
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/*** Register definitions for the 3c905 ***/
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enum Registers
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{
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regPowerMgmtCtrl_w = 0x7c, /** 905B Revision Only **/
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regUpMaxBurst_w = 0x7a, /** 905B Revision Only **/
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regDnMaxBurst_w = 0x78, /** 905B Revision Only **/
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regDebugControl_w = 0x74, /** 905B Revision Only **/
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regDebugData_l = 0x70, /** 905B Revision Only **/
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regRealTimeCnt_l = 0x40, /** Universal **/
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regUpBurstThresh_b = 0x3e, /** 905B Revision Only **/
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regUpPoll_b = 0x3d, /** 905B Revision Only **/
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regUpPriorityThresh_b = 0x3c, /** 905B Revision Only **/
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regUpListPtr_l = 0x38, /** Universal **/
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regCountdown_w = 0x36, /** Universal **/
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regFreeTimer_w = 0x34, /** Universal **/
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regUpPktStatus_l = 0x30, /** Universal with Exception, pg 130 **/
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regTxFreeThresh_b = 0x2f, /** 90X Revision Only **/
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regDnPoll_b = 0x2d, /** 905B Revision Only **/
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regDnPriorityThresh_b = 0x2c, /** 905B Revision Only **/
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regDnBurstThresh_b = 0x2a, /** 905B Revision Only **/
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regDnListPtr_l = 0x24, /** Universal with Exception, pg 107 **/
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regDmaCtrl_l = 0x20, /** Universal with Exception, pg 106 **/
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/** **/
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regIntStatusAuto_w = 0x1e, /** 905B Revision Only **/
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regTxStatus_b = 0x1b, /** Universal with Exception, pg 113 **/
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regTimer_b = 0x1a, /** Universal **/
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regTxPktId_b = 0x18, /** 905B Revision Only **/
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regCommandIntStatus_w = 0x0e, /** Universal (Command Variations) **/
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};
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/** following are windowed registers **/
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enum Registers7
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{
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regPowerMgmtEvent_7_w = 0x0c, /** 905B Revision Only **/
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regVlanEtherType_7_w = 0x04, /** 905B Revision Only **/
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regVlanMask_7_w = 0x00, /** 905B Revision Only **/
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};
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enum Registers6
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{
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regBytesXmittedOk_6_w = 0x0c, /** Universal **/
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regBytesRcvdOk_6_w = 0x0a, /** Universal **/
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regUpperFramesOk_6_b = 0x09, /** Universal **/
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regFramesDeferred_6_b = 0x08, /** Universal **/
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regFramesRecdOk_6_b = 0x07, /** Universal with Exceptions, pg 142 **/
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regFramesXmittedOk_6_b = 0x06, /** Universal **/
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regRxOverruns_6_b = 0x05, /** Universal **/
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regLateCollisions_6_b = 0x04, /** Universal **/
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regSingleCollisions_6_b = 0x03, /** Universal **/
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regMultipleCollisions_6_b = 0x02, /** Universal **/
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regSqeErrors_6_b = 0x01, /** Universal **/
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regCarrierLost_6_b = 0x00, /** Universal **/
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};
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enum Registers5
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{
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regIndicationEnable_5_w = 0x0c, /** Universal **/
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regInterruptEnable_5_w = 0x0a, /** Universal **/
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regTxReclaimThresh_5_b = 0x09, /** 905B Revision Only **/
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regRxFilter_5_b = 0x08, /** Universal **/
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regRxEarlyThresh_5_w = 0x06, /** Universal **/
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regTxStartThresh_5_w = 0x00, /** Universal **/
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};
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enum Registers4
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{
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regUpperBytesOk_4_b = 0x0d, /** Universal **/
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regBadSSD_4_b = 0x0c, /** Universal **/
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regMediaStatus_4_w = 0x0a, /** Universal with Exceptions, pg 201 **/
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regPhysicalMgmt_4_w = 0x08, /** Universal **/
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regNetworkDiagnostic_4_w = 0x06, /** Universal with Exceptions, pg 203 **/
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regFifoDiagnostic_4_w = 0x04, /** Universal with Exceptions, pg 196 **/
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regVcoDiagnostic_4_w = 0x02, /** Undocumented? **/
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};
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enum Registers3
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{
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regTxFree_3_w = 0x0c, /** Universal **/
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regRxFree_3_w = 0x0a, /** Universal with Exceptions, pg 125 **/
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regResetMediaOptions_3_w = 0x08, /** Media Options on B Revision, **/
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/** Reset Options on Non-B Revision **/
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regMacControl_3_w = 0x06, /** Universal with Exceptions, pg 199 **/
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regMaxPktSize_3_w = 0x04, /** 905B Revision Only **/
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regInternalConfig_3_l = 0x00, /** Universal, different bit **/
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/** definitions, pg 59 **/
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};
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enum Registers2
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{
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regResetOptions_2_w = 0x0c, /** 905B Revision Only **/
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regStationMask_2_3w = 0x06, /** Universal with Exceptions, pg 127 **/
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regStationAddress_2_3w = 0x00, /** Universal with Exceptions, pg 127 **/
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};
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enum Registers1
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{
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regRxStatus_1_w = 0x0a, /** 90X Revision Only, Pg 126 **/
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};
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enum Registers0
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{
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regEepromData_0_w = 0x0c, /** Universal **/
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regEepromCommand_0_w = 0x0a, /** Universal **/
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regBiosRomData_0_b = 0x08, /** 905B Revision Only **/
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regBiosRomAddr_0_l = 0x04, /** 905B Revision Only **/
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};
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/*** The names for the eight register windows ***/
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enum Windows
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{
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winPowerVlan7 = 0x07,
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winStatistics6 = 0x06,
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winTxRxControl5 = 0x05,
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winDiagnostics4 = 0x04,
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winTxRxOptions3 = 0x03,
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winAddressing2 = 0x02,
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winUnused1 = 0x01,
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winEepromBios0 = 0x00,
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};
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/*** Command definitions for the 3c90X ***/
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enum Commands
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{
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cmdGlobalReset = 0x00, /** Universal with Exceptions, pg 151 **/
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cmdSelectRegisterWindow = 0x01, /** Universal **/
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cmdEnableDcConverter = 0x02, /** **/
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cmdRxDisable = 0x03, /** **/
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cmdRxEnable = 0x04, /** Universal **/
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cmdRxReset = 0x05, /** Universal **/
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cmdStallCtl = 0x06, /** Universal **/
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cmdTxEnable = 0x09, /** Universal **/
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cmdTxDisable = 0x0A, /** **/
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cmdTxReset = 0x0B, /** Universal **/
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cmdRequestInterrupt = 0x0C, /** **/
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cmdAcknowledgeInterrupt = 0x0D, /** Universal **/
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cmdSetInterruptEnable = 0x0E, /** Universal **/
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cmdSetIndicationEnable = 0x0F, /** Universal **/
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cmdSetRxFilter = 0x10, /** Universal **/
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cmdSetRxEarlyThresh = 0x11, /** **/
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cmdSetTxStartThresh = 0x13, /** **/
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cmdStatisticsEnable = 0x15, /** **/
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cmdStatisticsDisable = 0x16, /** **/
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cmdDisableDcConverter = 0x17, /** **/
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cmdSetTxReclaimThresh = 0x18, /** **/
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cmdSetHashFilterBit = 0x19, /** **/
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};
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/*** Values for int status register bitmask **/
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#define INT_INTERRUPTLATCH (1<<0)
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#define INT_HOSTERROR (1<<1)
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#define INT_TXCOMPLETE (1<<2)
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#define INT_RXCOMPLETE (1<<4)
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#define INT_RXEARLY (1<<5)
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#define INT_INTREQUESTED (1<<6)
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#define INT_UPDATESTATS (1<<7)
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#define INT_LINKEVENT (1<<8)
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#define INT_DNCOMPLETE (1<<9)
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#define INT_UPCOMPLETE (1<<10)
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#define INT_CMDINPROGRESS (1<<12)
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#define INT_WINDOWNUMBER (7<<13)
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/*** TX descriptor ***/
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typedef struct
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{
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unsigned int DnNextPtr;
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unsigned int FrameStartHeader;
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unsigned int HdrAddr;
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unsigned int HdrLength;
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unsigned int DataAddr;
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unsigned int DataLength;
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}
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TXD;
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/*** RX descriptor ***/
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typedef struct
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{
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unsigned int UpNextPtr;
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unsigned int UpPktStatus;
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unsigned int DataAddr;
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unsigned int DataLength;
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}
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RXD;
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/*** Global variables ***/
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static struct
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{
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unsigned char isBrev;
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unsigned char CurrentWindow;
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unsigned int IOAddr;
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unsigned char HWAddr[6];
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TXD TransmitDPD;
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RXD ReceiveUPD;
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}
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INF_3C90X;
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/*** a3c90x_internal_IssueCommand: sends a command to the 3c90x card
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***/
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static int
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a3c90x_internal_IssueCommand(int ioaddr, int cmd, int param)
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{
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unsigned int val;
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/** Build the cmd. **/
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val = cmd;
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val <<= 11;
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val |= param;
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/** Send the cmd to the cmd register **/
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outw(val, ioaddr + regCommandIntStatus_w);
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/** Wait for the cmd to complete, if necessary **/
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while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
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return 0;
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}
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/*** a3c90x_internal_SetWindow: selects a register window set.
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***/
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static int
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a3c90x_internal_SetWindow(int ioaddr, int window)
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{
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/** Window already as set? **/
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if (INF_3C90X.CurrentWindow == window) return 0;
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/** Issue the window command. **/
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a3c90x_internal_IssueCommand(ioaddr, cmdSelectRegisterWindow, window);
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INF_3C90X.CurrentWindow = window;
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return 0;
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}
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/*** a3c90x_internal_ReadEeprom - read data from the serial eeprom.
|
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***/
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static unsigned short
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a3c90x_internal_ReadEeprom(int ioaddr, int address)
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{
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unsigned short val;
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/** Select correct window **/
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a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winEepromBios0);
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/** Make sure the eeprom isn't busy **/
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while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
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||||
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/** Read the value. **/
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outw(address + ((0x02)<<6), ioaddr + regEepromCommand_0_w);
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while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
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val = inw(ioaddr + regEepromData_0_w);
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return val;
|
||||
}
|
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|
||||
|
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/*** a3c90x_internal_WriteEepromWord - write a physical word of
|
||||
*** data to the onboard serial eeprom (not the BIOS prom, but the
|
||||
*** nvram in the card that stores, among other things, the MAC
|
||||
*** address).
|
||||
***/
|
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static int
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a3c90x_internal_WriteEepromWord(int ioaddr, int address, unsigned short value)
|
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{
|
||||
/** Select register window **/
|
||||
a3c90x_internal_SetWindow(ioaddr, winEepromBios0);
|
||||
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||||
/** Verify Eeprom not busy **/
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while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
|
||||
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/** Issue WriteEnable, and wait for completion. **/
|
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outw(0x30, ioaddr + regEepromCommand_0_w);
|
||||
while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
|
||||
|
||||
/** Issue EraseRegister, and wait for completion. **/
|
||||
outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
|
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while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
|
||||
|
||||
/** Send the new data to the eeprom, and wait for completion. **/
|
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outw(value, ioaddr + regEepromData_0_w);
|
||||
outw(0x30, ioaddr + regEepromCommand_0_w);
|
||||
while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
|
||||
|
||||
/** Burn the new data into the eeprom, and wait for completion. **/
|
||||
outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
|
||||
while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*** a3c90x_internal_WriteEeprom - write data to the serial eeprom,
|
||||
*** and re-compute the eeprom checksum.
|
||||
***/
|
||||
static int
|
||||
a3c90x_internal_WriteEeprom(int ioaddr, int address, unsigned short value)
|
||||
{
|
||||
int cksum = 0,v;
|
||||
int i;
|
||||
int maxAddress, cksumAddress;
|
||||
|
||||
if (INF_3C90X.isBrev)
|
||||
{
|
||||
maxAddress=0x1f;
|
||||
cksumAddress=0x20;
|
||||
}
|
||||
else
|
||||
{
|
||||
maxAddress=0x16;
|
||||
cksumAddress=0x17;
|
||||
}
|
||||
|
||||
/** Write the value. **/
|
||||
if (a3c90x_internal_WriteEepromWord(ioaddr, address, value) == -1)
|
||||
return -1;
|
||||
|
||||
/** Recompute the checksum. **/
|
||||
for(i=0;i<=maxAddress;i++)
|
||||
{
|
||||
v = a3c90x_internal_ReadEeprom(ioaddr, i);
|
||||
cksum ^= (v & 0xFF);
|
||||
cksum ^= ((v>>8) & 0xFF);
|
||||
}
|
||||
/** Write the checksum to the location in the eeprom **/
|
||||
if (a3c90x_internal_WriteEepromWord(ioaddr, cksumAddress, cksum) == -1)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*** a3c90x_reset: exported function that resets the card to its default
|
||||
*** state. This is so the Linux driver can re-set the card up the way
|
||||
*** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will
|
||||
*** not alter the selected transceiver that we used to download the boot
|
||||
*** image.
|
||||
***/
|
||||
static void
|
||||
a3c90x_reset(struct nic *nic)
|
||||
{
|
||||
int cfg;
|
||||
|
||||
#ifdef CFG_3C90X_PRESERVE_XCVR
|
||||
/** Read the current InternalConfig value. **/
|
||||
a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
|
||||
cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
|
||||
#endif
|
||||
|
||||
/** Send the reset command to the card **/
|
||||
printf("Issuing RESET:\n");
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdGlobalReset, 0);
|
||||
|
||||
/** wait for reset command to complete **/
|
||||
while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
|
||||
|
||||
/** global reset command resets station mask, non-B revision cards
|
||||
** require explicit reset of values
|
||||
**/
|
||||
a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
|
||||
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
|
||||
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
|
||||
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
|
||||
|
||||
#ifdef CFG_3C90X_PRESERVE_XCVR
|
||||
/** Re-set the original InternalConfig value from before reset **/
|
||||
a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
|
||||
outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
|
||||
|
||||
/** enable DC converter for 10-Base-T **/
|
||||
if ((cfg&0x0300) == 0x0300)
|
||||
{
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Issue transmit reset, wait for command completion **/
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0);
|
||||
while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
|
||||
;
|
||||
if (! INF_3C90X.isBrev)
|
||||
outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
|
||||
|
||||
/**
|
||||
** reset of the receiver on B-revision cards re-negotiates the link
|
||||
** takes several seconds (a computer eternity)
|
||||
**/
|
||||
if (INF_3C90X.isBrev)
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
|
||||
else
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
|
||||
while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
|
||||
;
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
|
||||
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
|
||||
cmdSetInterruptEnable, 0);
|
||||
/** enable rxComplete and txComplete **/
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
|
||||
cmdSetIndicationEnable, 0x0014);
|
||||
/** acknowledge any pending status flags **/
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
|
||||
cmdAcknowledgeInterrupt, 0x661);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*** a3c90x_transmit: exported function that transmits a packet. Does not
|
||||
*** return any particular status. Parameters are:
|
||||
*** d[6] - destination address, ethernet;
|
||||
*** t - protocol type (ARP, IP, etc);
|
||||
*** s - size of the non-header part of the packet that needs transmitted;
|
||||
*** p - the pointer to the packet data itself.
|
||||
***/
|
||||
static void
|
||||
a3c90x_transmit(struct nic *nic, char *d, unsigned int t,
|
||||
unsigned int s, char *p)
|
||||
{
|
||||
|
||||
struct eth_hdr
|
||||
{
|
||||
unsigned char dst_addr[6];
|
||||
unsigned char src_addr[6];
|
||||
unsigned short type;
|
||||
} hdr;
|
||||
|
||||
unsigned char status;
|
||||
unsigned timeout, i, retries;
|
||||
|
||||
for (retries=0; retries < XMIT_RETRIES ; retries++)
|
||||
{
|
||||
/** Stall the download engine **/
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 2);
|
||||
|
||||
/** Make sure the card is not waiting on us **/
|
||||
inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
|
||||
inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
|
||||
|
||||
while (inw(INF_3C90X.IOAddr+regCommandIntStatus_w) &
|
||||
INT_CMDINPROGRESS)
|
||||
;
|
||||
|
||||
/** Set the ethernet packet type **/
|
||||
hdr.type = htons(t);
|
||||
|
||||
/** Copy the destination address **/
|
||||
memcpy(hdr.dst_addr, d, 6);
|
||||
|
||||
/** Copy our MAC address **/
|
||||
memcpy(hdr.src_addr, INF_3C90X.HWAddr, 6);
|
||||
|
||||
/** Setup the DPD (download descriptor) **/
|
||||
INF_3C90X.TransmitDPD.DnNextPtr = 0;
|
||||
/** set notification for transmission completion (bit 15) **/
|
||||
INF_3C90X.TransmitDPD.FrameStartHeader = (s + sizeof(hdr)) | 0x8000;
|
||||
INF_3C90X.TransmitDPD.HdrAddr = virt_to_bus(&hdr);
|
||||
INF_3C90X.TransmitDPD.HdrLength = sizeof(hdr);
|
||||
INF_3C90X.TransmitDPD.DataAddr = virt_to_bus(p);
|
||||
INF_3C90X.TransmitDPD.DataLength = s + (1<<31);
|
||||
|
||||
/** Send the packet **/
|
||||
outl(virt_to_bus(&(INF_3C90X.TransmitDPD)),
|
||||
INF_3C90X.IOAddr + regDnListPtr_l);
|
||||
|
||||
/** End Stall and Wait for upload to complete. **/
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 3);
|
||||
while(inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0)
|
||||
;
|
||||
|
||||
/** Wait for NIC Transmit to Complete **/
|
||||
timeout=TIME_OUT;
|
||||
while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004) &&
|
||||
--timeout)
|
||||
for(i=0;i<TIME_OUT;i++);
|
||||
|
||||
if (timeout==0)
|
||||
{
|
||||
printf("3C90X: Transmission Timeout\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
status = inb(INF_3C90X.IOAddr + regTxStatus_b);
|
||||
|
||||
/** acknowledge transmit interrupt by writing status **/
|
||||
outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
|
||||
|
||||
/** successful completion (sans "interrupt Requested" bit) **/
|
||||
if ((status & 0xbf) == 0x80)
|
||||
return;
|
||||
|
||||
printf("3C90X: Status (%x)\n", status);
|
||||
/** check error codes **/
|
||||
if (status & 0x02)
|
||||
{
|
||||
printf("3C90X: Transmitter Reclaim Error (%x)\n", status);
|
||||
a3c90x_reset(NULL);
|
||||
}
|
||||
else if (status & 0x04)
|
||||
{
|
||||
printf("3C90X: Transmitter Status Overflow (%x)\n", status);
|
||||
for (i=0; i<32; i++)
|
||||
outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
|
||||
/** must re-enable after max collisions before re-issuing tx **/
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
|
||||
}
|
||||
else if (status & 0x08)
|
||||
{
|
||||
printf("3C90X: Transmitter Max Collisions (%x)\n", status);
|
||||
/** must re-enable after max collisions before re-issuing tx **/
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
|
||||
}
|
||||
else if (status & 0x10)
|
||||
{
|
||||
printf("3C90X: Transmitter Underrun (%x)\n", status);
|
||||
a3c90x_reset(NULL);
|
||||
}
|
||||
else if (status & 0x20)
|
||||
{
|
||||
printf("3C90X: Transmitter Jabber (%x)\n", status);
|
||||
a3c90x_reset(NULL);
|
||||
}
|
||||
else if ((status & 0x80) != 0x80)
|
||||
{
|
||||
printf("3C90X: Internal Error - Incomplete Transmission (%x)\n",
|
||||
status);
|
||||
a3c90x_reset(NULL);
|
||||
}
|
||||
}
|
||||
|
||||
/** failed after RETRY attempts **/
|
||||
printf("Failed to send after %d retries\n", retries);
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*** a3c90x_poll: exported routine that waits for a certain length of time
|
||||
*** for a packet, and if it sees none, returns 0. This routine should
|
||||
*** copy the packet to nic->packet if it gets a packet and set the size
|
||||
*** in nic->packetlen. Return 1 if a packet was found.
|
||||
***/
|
||||
static int
|
||||
a3c90x_poll(struct nic *nic)
|
||||
{
|
||||
int i, errcode;
|
||||
|
||||
if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0010))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/** we don't need to acknowledge rxComplete -- the upload engine
|
||||
** does it for us.
|
||||
**/
|
||||
|
||||
/** Build the up-load descriptor **/
|
||||
INF_3C90X.ReceiveUPD.UpNextPtr = 0;
|
||||
INF_3C90X.ReceiveUPD.UpPktStatus = 0;
|
||||
INF_3C90X.ReceiveUPD.DataAddr = virt_to_bus(nic->packet);
|
||||
INF_3C90X.ReceiveUPD.DataLength = 1536 + (1<<31);
|
||||
|
||||
/** Submit the upload descriptor to the NIC **/
|
||||
outl(virt_to_bus(&(INF_3C90X.ReceiveUPD)),
|
||||
INF_3C90X.IOAddr + regUpListPtr_l);
|
||||
|
||||
/** Wait for upload completion (upComplete(15) or upError (14)) **/
|
||||
for(i=0;i<40000;i++);
|
||||
while((INF_3C90X.ReceiveUPD.UpPktStatus & ((1<<14) | (1<<15))) == 0)
|
||||
for(i=0;i<40000;i++);
|
||||
|
||||
/** Check for Error (else we have good packet) **/
|
||||
if (INF_3C90X.ReceiveUPD.UpPktStatus & (1<<14))
|
||||
{
|
||||
errcode = INF_3C90X.ReceiveUPD.UpPktStatus;
|
||||
if (errcode & (1<<16))
|
||||
printf("3C90X: Receiver Overrun (%x)\n",errcode>>16);
|
||||
else if (errcode & (1<<17))
|
||||
printf("3C90X: Runt Frame (%x)\n",errcode>>16);
|
||||
else if (errcode & (1<<18))
|
||||
printf("3C90X: Alignment Error (%x)\n",errcode>>16);
|
||||
else if (errcode & (1<<19))
|
||||
printf("3C90X: CRC Error (%x)\n",errcode>>16);
|
||||
else if (errcode & (1<<20))
|
||||
printf("3C90X: Oversized Frame (%x)\n",errcode>>16);
|
||||
else
|
||||
printf("3C90X: Packet error (%x)\n",errcode>>16);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/** Ok, got packet. Set length in nic->packetlen. **/
|
||||
nic->packetlen = (INF_3C90X.ReceiveUPD.UpPktStatus & 0x1FFF);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*** a3c90x_disable: exported routine to disable the card. What's this for?
|
||||
*** the eepro100.c driver didn't have one, so I just left this one empty too.
|
||||
*** Ideas anyone?
|
||||
***/
|
||||
static void
|
||||
a3c90x_disable(struct nic *nic)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
|
||||
*** initialization. If this routine is called, the pci functions did find the
|
||||
*** card. We just have to init it here.
|
||||
***/
|
||||
struct nic*
|
||||
a3c90x_probe(struct nic *nic, unsigned short *probeaddrs)
|
||||
{
|
||||
int i, j, to, v, c;
|
||||
unsigned short eeprom[0x21];
|
||||
unsigned int cfg;
|
||||
unsigned int mopt;
|
||||
unsigned short linktype;
|
||||
|
||||
if (probeaddrs == 0 || probeaddrs[0] == 0)
|
||||
return 0;
|
||||
|
||||
INF_3C90X.IOAddr = probeaddrs[0] & ~3;
|
||||
INF_3C90X.CurrentWindow = 255;
|
||||
switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
|
||||
{
|
||||
case 0x9000: /** 10 Base TPO **/
|
||||
case 0x9001: /** 10/100 T4 **/
|
||||
case 0x9050: /** 10/100 TPO **/
|
||||
case 0x9051: /** 10 Base Combo **/
|
||||
INF_3C90X.isBrev = 0;
|
||||
break;
|
||||
|
||||
case 0x9004: /** 10 Base TPO **/
|
||||
case 0x9005: /** 10 Base Combo **/
|
||||
case 0x9006: /** 10 Base TPO and Base2 **/
|
||||
case 0x900A: /** 10 Base FL **/
|
||||
case 0x9055: /** 10/100 TPO **/
|
||||
case 0x9056: /** 10/100 T4 **/
|
||||
case 0x905A: /** 10 Base FX **/
|
||||
default:
|
||||
INF_3C90X.isBrev = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
/** Load the EEPROM contents **/
|
||||
if (INF_3C90X.isBrev)
|
||||
{
|
||||
for(i=0;i<=0x20;i++)
|
||||
{
|
||||
eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
|
||||
}
|
||||
|
||||
/** Set xcvrSelect in InternalConfig in eeprom. **/
|
||||
/* only necessary for 3c905b revision cards with boot PROM bug!!! */
|
||||
a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x13, 0x0160);
|
||||
|
||||
#ifdef CFG_3C90X_XCVR
|
||||
if (CFG_3C90X_XCVR == 255)
|
||||
{
|
||||
/** Clear the LanWorks register **/
|
||||
a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
/** Set the selected permanent-xcvrSelect in the
|
||||
** LanWorks register
|
||||
**/
|
||||
a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16,
|
||||
XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
for(i=0;i<=0x17;i++)
|
||||
{
|
||||
eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
|
||||
}
|
||||
}
|
||||
|
||||
/** Print identification message **/
|
||||
printf("\n\n3C90X Driver 2.00 "
|
||||
"Copyright 1999 LightSys Technology Services, Inc.\n"
|
||||
"Portions Copyright 1999 Steve Smith\n");
|
||||
printf("Provided with ABSOLUTELY NO WARRANTY.\n");
|
||||
printf("-------------------------------------------------------"
|
||||
"------------------------\n");
|
||||
|
||||
/** Retrieve the Hardware address and print it on the screen. **/
|
||||
INF_3C90X.HWAddr[0] = eeprom[0]>>8;
|
||||
INF_3C90X.HWAddr[1] = eeprom[0]&0xFF;
|
||||
INF_3C90X.HWAddr[2] = eeprom[1]>>8;
|
||||
INF_3C90X.HWAddr[3] = eeprom[1]&0xFF;
|
||||
INF_3C90X.HWAddr[4] = eeprom[2]>>8;
|
||||
INF_3C90X.HWAddr[5] = eeprom[2]&0xFF;
|
||||
printf("MAC Address = %b:%b:%b:%b:%b:%b\n",
|
||||
INF_3C90X.HWAddr[0],INF_3C90X.HWAddr[1],INF_3C90X.HWAddr[2],
|
||||
INF_3C90X.HWAddr[3],INF_3C90X.HWAddr[4],INF_3C90X.HWAddr[5]);
|
||||
|
||||
/** Program the MAC address into the station address registers **/
|
||||
a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
|
||||
outw(htons(eeprom[0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
|
||||
outw(htons(eeprom[1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
|
||||
outw(htons(eeprom[2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
|
||||
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
|
||||
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
|
||||
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
|
||||
|
||||
/** Fill in our entry in the etherboot arp table **/
|
||||
for(i=0;i<6;i++) nic->node_addr[i] = (eeprom[i/2] >> (8*((i&1)^1))) & 0xff;
|
||||
|
||||
/** Read the media options register, print a message and set default
|
||||
** xcvr.
|
||||
**
|
||||
** Uses Media Option command on B revision, Reset Option on non-B
|
||||
** revision cards -- same register address
|
||||
**/
|
||||
a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
|
||||
mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w);
|
||||
|
||||
/** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/
|
||||
if (! INF_3C90X.isBrev)
|
||||
{
|
||||
mopt &= 0x7F;
|
||||
}
|
||||
|
||||
printf("Connectors present: ");
|
||||
c = 0;
|
||||
linktype = 0x0008;
|
||||
if (mopt & 0x01)
|
||||
{
|
||||
printf("%s100Base-T4",(c++)?", ":"");
|
||||
linktype = 0x0006;
|
||||
}
|
||||
if (mopt & 0x04)
|
||||
{
|
||||
printf("%s100Base-FX",(c++)?", ":"");
|
||||
linktype = 0x0005;
|
||||
}
|
||||
if (mopt & 0x10)
|
||||
{
|
||||
printf("%s10Base-2",(c++)?", ":"");
|
||||
linktype = 0x0003;
|
||||
}
|
||||
if (mopt & 0x20)
|
||||
{
|
||||
printf("%sAUI",(c++)?", ":"");
|
||||
linktype = 0x0001;
|
||||
}
|
||||
if (mopt & 0x40)
|
||||
{
|
||||
printf("%sMII",(c++)?", ":"");
|
||||
linktype = 0x0006;
|
||||
}
|
||||
if ((mopt & 0xA) == 0xA)
|
||||
{
|
||||
printf("%s10Base-T / 100Base-TX",(c++)?", ":"");
|
||||
linktype = 0x0008;
|
||||
}
|
||||
else if ((mopt & 0xA) == 0x2)
|
||||
{
|
||||
printf("%s100Base-TX",(c++)?", ":"");
|
||||
linktype = 0x0008;
|
||||
}
|
||||
else if ((mopt & 0xA) == 0x8)
|
||||
{
|
||||
printf("%s10Base-T",(c++)?", ":"");
|
||||
linktype = 0x0008;
|
||||
}
|
||||
printf(".\n");
|
||||
|
||||
/** Determine transceiver type to use, depending on value stored in
|
||||
** eeprom 0x16
|
||||
**/
|
||||
if (INF_3C90X.isBrev)
|
||||
{
|
||||
if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC)
|
||||
{
|
||||
/** User-defined **/
|
||||
linktype = eeprom[0x16] & 0x000F;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef CFG_3C90X_XCVR
|
||||
if (CFG_3C90X_XCVR != 255)
|
||||
linktype = CFG_3C90X_XCVR;
|
||||
#endif // CFG_3C90X_XCVR
|
||||
|
||||
/** I don't know what MII MAC only mode is!!! **/
|
||||
if (linktype == 0x0009)
|
||||
{
|
||||
if (INF_3C90X.isBrev)
|
||||
printf("WARNING: MII External MAC Mode only supported on B-revision "
|
||||
"cards!!!!\nFalling Back to MII Mode\n");
|
||||
linktype = 0x0006;
|
||||
}
|
||||
}
|
||||
|
||||
/** enable DC converter for 10-Base-T **/
|
||||
if (linktype == 0x0003)
|
||||
{
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
|
||||
}
|
||||
|
||||
/** Set the link to the type we just determined. **/
|
||||
a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
|
||||
cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
|
||||
cfg &= ~(0xF<<20);
|
||||
cfg |= (linktype<<20);
|
||||
outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
|
||||
|
||||
/** Now that we set the xcvr type, reset the Tx and Rx, re-enable. **/
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0x00);
|
||||
while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
|
||||
;
|
||||
|
||||
if (!INF_3C90X.isBrev)
|
||||
outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
|
||||
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
|
||||
|
||||
/**
|
||||
** reset of the receiver on B-revision cards re-negotiates the link
|
||||
** takes several seconds (a computer eternity)
|
||||
**/
|
||||
if (INF_3C90X.isBrev)
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
|
||||
else
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
|
||||
while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
|
||||
;
|
||||
|
||||
/** Set the RX filter = receive only individual pkts & bcast. **/
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x04);
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
|
||||
|
||||
|
||||
/**
|
||||
** set Indication and Interrupt flags , acknowledge any IRQ's
|
||||
**/
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
|
||||
cmdSetIndicationEnable, 0x0014);
|
||||
a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
|
||||
cmdAcknowledgeInterrupt, 0x661);
|
||||
|
||||
/** Set our exported functions **/
|
||||
nic->reset = a3c90x_reset;
|
||||
nic->poll = a3c90x_poll;
|
||||
nic->transmit = a3c90x_transmit;
|
||||
nic->disable = a3c90x_disable;
|
||||
|
||||
return nic;
|
||||
}
|
||||
|
||||
|
||||
Reference in new issue
Block a user