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update the network support to etherboot-4.6.4.
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@@ -38,33 +38,33 @@
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* Some global constants
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*/
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#define TX_INIT_RATE 16
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#define TX_INIT_MAX_RATE 64
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#define RX_INIT_LATENCY 64
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#define RX_INIT_EARLY_THRESH 64
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#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */
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#define MIN_RX_EARLY_THRESHL 4
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#define TX_INIT_RATE 16
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#define TX_INIT_MAX_RATE 64
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#define RX_INIT_LATENCY 64
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#define RX_INIT_EARLY_THRESH 64
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#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */
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#define MIN_RX_EARLY_THRESHL 4
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#define EEPROMSIZE 0x40
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#define MAX_EEPROMBUSY 1000
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#define EP_LAST_TAG 0xd7
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#define EP_MAX_BOARDS 16
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#define EP_ID_PORT 0x100
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#define EEPROMSIZE 0x40
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#define MAX_EEPROMBUSY 1000
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#define EP_LAST_TAG 0xd7
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#define EP_MAX_BOARDS 16
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#define EP_ID_PORT 0x100
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/*
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* some macros to acces long named fields
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*/
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#define IS_BASE (eth_nic_base)
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#define BASE (eth_nic_base)
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#define BASE (eth_nic_base)
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/*
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* Commands to read/write EEPROM trough EEPROM command register (Window 0,
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* Offset 0xa)
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*/
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#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
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#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
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#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
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#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
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#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
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#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
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#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
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#define EEPROM_BUSY (1<<15)
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#define EEPROM_TST_MODE (1<<14)
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@@ -73,10 +73,10 @@
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* Some short functions, worth to let them be a macro
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*/
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#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
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#define GO_WINDOW(x) outw(WINDOW_SELECT|(x), BASE+EP_COMMAND)
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#define GO_WINDOW(x) outw(WINDOW_SELECT|(x), BASE+EP_COMMAND)
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/**************************************************************************
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* *
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*
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* These define the EEPROM data structure. They are used in the probe
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* function to verify the existance of the adapter after having sent
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* the ID_Sequence.
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@@ -94,12 +94,12 @@
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#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
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/**************************************************************************
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* *
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* These are the registers for the 3Com 3c509 and their bit patterns when *
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* applicable. They have been taken out the the "EtherLink III Parallel *
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* Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
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* from 3com. *
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* *
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*
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* These are the registers for the 3Com 3c509 and their bit patterns when
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* applicable. They have been taken out the the "EtherLink III Parallel
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* Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual
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* from 3com.
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*
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**************************************************************************/
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#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a
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@@ -276,7 +276,7 @@
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#define S_RX_EARLY (unsigned short) (0x20)
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#define S_INT_RQD (unsigned short) (0x40)
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#define S_UPD_STATS (unsigned short) (0x80)
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#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\
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#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\
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S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
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#define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000)
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@@ -297,14 +297,14 @@
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*
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* 10-0: RX Bytes (0-1514)
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*/
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#define ERR_RX_INCOMPLETE (unsigned short) (0x1<<15)
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#define ERR_RX (unsigned short) (0x1<<14)
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#define ERR_RX_OVERRUN (unsigned short) (0x8<<11)
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#define ERR_RX_RUN_PKT (unsigned short) (0xb<<11)
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#define ERR_RX_ALIGN (unsigned short) (0xc<<11)
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#define ERR_RX_CRC (unsigned short) (0xd<<11)
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#define ERR_RX_OVERSIZE (unsigned short) (0x9<<11)
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#define ERR_RX_DRIBBLE (unsigned short) (0x2<<11)
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#define ERR_RX_INCOMPLETE (unsigned short) (0x1<<15)
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#define ERR_RX (unsigned short) (0x1<<14)
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#define ERR_RX_OVERRUN (unsigned short) (0x8<<11)
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#define ERR_RX_RUN_PKT (unsigned short) (0xb<<11)
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#define ERR_RX_ALIGN (unsigned short) (0xc<<11)
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#define ERR_RX_CRC (unsigned short) (0xd<<11)
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#define ERR_RX_OVERSIZE (unsigned short) (0x9<<11)
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#define ERR_RX_DRIBBLE (unsigned short) (0x2<<11)
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/*
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* FIFO Registers.
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@@ -336,13 +336,13 @@
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* Window 0/Port 04
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*/
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/* Read */
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#define IS_AUI (1<<13)
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#define IS_BNC (1<<12)
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#define IS_UTP (1<<9)
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#define IS_AUI (1<<13)
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#define IS_BNC (1<<12)
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#define IS_UTP (1<<9)
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/* Write */
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#define ENABLE_DRQ_IRQ 0x0001
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#define W0_P4_CMD_RESET_ADAPTER 0x4
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#define W0_P4_CMD_ENABLE_ADAPTER 0x1
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#define W0_P4_CMD_RESET_ADAPTER 0x4
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#define W0_P4_CMD_ENABLE_ADAPTER 0x1
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/*
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* Media type and status.
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* Window 4/Port 0A
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@@ -368,26 +368,26 @@
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/*
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* Misc defines for various things.
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*/
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#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */
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#define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
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#define PROD_ID 0x9150
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#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */
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#define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
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#define PROD_ID 0x9150
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#define AUI 0x1
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#define BNC 0x2
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#define UTP 0x4
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#define AUI 0x1
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#define BNC 0x2
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#define UTP 0x4
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#define RX_BYTES_MASK (unsigned short) (0x07ff)
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/* EISA support */
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#define EP_EISA_START 0x1000
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#define EP_EISA_W0 0x0c80
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#define EP_EISA_START 0x1000
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#define EP_EISA_W0 0x0c80
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#ifdef INCLUDE_3C529
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#ifdef INCLUDE_3C529
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/* MCA support */
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#define MCA_MOTHERBOARD_SETUP_REG 0x94
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#define MCA_ADAPTER_SETUP_REG 0x96
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#define MCA_MAX_SLOT_NR 8
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#define MCA_POS_REG(n) (0x100+(n))
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#define MCA_MOTHERBOARD_SETUP_REG 0x94
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#define MCA_ADAPTER_SETUP_REG 0x96
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#define MCA_MAX_SLOT_NR 8
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#define MCA_POS_REG(n) (0x100+(n))
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#endif
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/*
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