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libgcrypt: Import libgcrypt 1.11
We currently use an old version of libgcrypt which results in us having fewer ciphers and missing on many other improvements. Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com>
This commit is contained in:
Vladimir Serbinenko authored and Daniel Kiper committed
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@@ -0,0 +1,383 @@
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/* sha512-armv8-aarch64-ce.S - ARM/CE accelerated SHA-512 transform function
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* Copyright (C) 2022 Jussi Kivilinna <jussi.kivilinna@iki.fi>
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*
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* This file is part of Libgcrypt.
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*
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* Libgcrypt is free software; you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as
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* published by the Free Software Foundation; either version 2.1 of
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* the License, or (at your option) any later version.
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*
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* Libgcrypt is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "asm-common-aarch64.h"
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#if defined(__AARCH64EL__) && \
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defined(HAVE_COMPATIBLE_GCC_AARCH64_PLATFORM_AS) && \
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defined(HAVE_GCC_INLINE_ASM_AARCH64_SHA3_SHA512_SM3_SM4) && \
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defined(USE_SHA512)
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.arch armv8.2-a+sha3+sm4
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.text
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/* Register macros */
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#define Qv0 q0
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#define Qv1 q1
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#define Qv2 q2
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#define Qv3 q3
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#define Qv4 q4
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#define vT0 v5
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#define vT1 v6
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#define QvT1 q6
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#define vT2 v7
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#define vT3 v16
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#define vH01 v17
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#define vH23 v18
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#define vH45 v19
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#define vH67 v20
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#define vW0 v21
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#define vW1 v22
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#define vW2 v23
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#define vW3 v24
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#define vW4 v25
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#define vW5 v26
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#define vW6 v27
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#define vW7 v28
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#define vK0 v29
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#define vK1 v30
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#define vK2 v31
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/* Round macros */
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#define _(...) /*_*/
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#define do_add(a, b) add a.2d, a.2d, b.2d;
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#define load_k_3() ld1 {vK0.2d-vK2.2d}, [x3], #48;
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#define load_k_last() ld1 {vK0.2d}, [x3];
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#define load_msg1(...) \
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ld1 {vW0.16b-vW3.16b}, [x1], #64;
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#define load_msg2(...) \
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rev64 vW0.16b, vW0.16b;
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#define load_msg3(...) \
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rev64 vW1.16b, vW1.16b;
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#define load_msg4(...) \
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ld1 {vW4.16b-vW7.16b}, [x1], #64;
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#define load_msg5(...) \
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rev64 vW2.16b, vW2.16b;
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#define load_msg6(...) \
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rev64 vW3.16b, vW3.16b;
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#define load_msg7(...) \
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rev64 vW4.16b, vW4.16b;
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#define load_msg8(...) \
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rev64 vW5.16b, vW5.16b;
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#define load_msg9(...) \
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rev64 vW6.16b, vW6.16b;
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#define load_msg10(...) \
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rev64 vW7.16b, vW7.16b;
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#define schedule1(w0, w1, w2, w3, w4, w5, w6, w7) \
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sha512su0 w0.2d, w1.2d; \
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#define schedule2(w0, w1, w2, w3, w4, w5, w6, w7) \
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ext vT2.16b, w4.16b, w5.16b, #8; \
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sha512su1 w0.2d, w7.2d, vT2.2d;
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#define do_round2(ab, cd, ef, gh, cd_out, \
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load_nextk_op, k, \
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sched_op1, sched_op2, w0, w1, w2, w3, w4, w5, w6, w7) \
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add vT3.2d, k.2d, w0.2d; \
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load_nextk_op(); \
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ext vT1.16b, ef.16b, gh.16b, #8; \
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ext vT3.16b, vT3.16b, vT3.16b, #8; \
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ext vT0.16b, cd.16b, ef.16b, #8; \
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add gh.2d, gh.2d, vT3.2d; \
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sched_op1(w0, w1, w2, w3, w4, w5, w6, w7); \
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sha512h Q##gh, Q##vT1, vT0.2d; \
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sched_op2(w0, w1, w2, w3, w4, w5, w6, w7); \
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add cd_out.2d, gh.2d, cd.2d; \
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sha512h2 Q##gh, Q##cd, ab.2d; \
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/* Other functional macros */
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#undef CLEAR_REG
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#define CLEAR_REG(reg, ...) movi reg.16b, #0;
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/*
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* unsigned int
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* _gcry_sha512_transform_armv8_ce (u64 state[8], const void *input_data,
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* size_t num_blks, const u64 k[80])
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*/
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.align 4
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.globl _gcry_sha512_transform_armv8_ce
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ELF(.type _gcry_sha512_transform_armv8_ce,%function;)
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_gcry_sha512_transform_armv8_ce:
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/* input:
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* x0: ctx, CTX
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* x1: data (128*nblks bytes)
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* x2: nblks
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* x3: k table
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*/
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CFI_STARTPROC()
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cbz x2, .Ldo_nothing
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mov x4, x3
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ld1 {vH01.2d-vH67.2d}, [x0] /* load state */
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load_msg1()
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mov v0.16b, vH01.16b
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mov v1.16b, vH23.16b
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load_k_3()
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load_msg2()
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load_msg3()
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load_msg4()
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mov v2.16b, vH45.16b
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mov v3.16b, vH67.16b
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load_msg5()
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load_msg6()
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load_msg7()
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load_msg8()
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load_msg9()
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load_msg10()
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.Loop:
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sub x2, x2, #1
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# rounds 1-16
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do_round2(v0, v1, v2, v3, v4,
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_, vK0,
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schedule1, schedule2, vW0, vW1, vW2, vW3, vW4, vW5, vW6, vW7)
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do_round2(v3, v0, v4, v2, v1,
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_, vK1,
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schedule1, schedule2, vW1, vW2, vW3, vW4, vW5, vW6, vW7, vW0)
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do_round2(v2, v3, v1, v4, v0,
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load_k_3, vK2,
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schedule1, schedule2, vW2, vW3, vW4, vW5, vW6, vW7, vW0, vW1)
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do_round2(v4, v2, v0, v1, v3,
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_, vK0,
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schedule1, schedule2, vW3, vW4, vW5, vW6, vW7, vW0, vW1, vW2)
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do_round2(v1, v4, v3, v0, v2,
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_, vK1,
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schedule1, schedule2, vW4, vW5, vW6, vW7, vW0, vW1, vW2, vW3)
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do_round2(v0, v1, v2, v3, v4,
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load_k_3, vK2,
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schedule1, schedule2, vW5, vW6, vW7, vW0, vW1, vW2, vW3, vW4)
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do_round2(v3, v0, v4, v2, v1,
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_, vK0,
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schedule1, schedule2, vW6, vW7, vW0, vW1, vW2, vW3, vW4, vW5)
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do_round2(v2, v3, v1, v4, v0,
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_, vK1,
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schedule1, schedule2, vW7, vW0, vW1, vW2, vW3, vW4, vW5, vW6)
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# rounds 17-32
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do_round2(v4, v2, v0, v1, v3,
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load_k_3, vK2,
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schedule1, schedule2, vW0, vW1, vW2, vW3, vW4, vW5, vW6, vW7)
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do_round2(v1, v4, v3, v0, v2,
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_, vK0,
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schedule1, schedule2, vW1, vW2, vW3, vW4, vW5, vW6, vW7, vW0)
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do_round2(v0, v1, v2, v3, v4,
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_, vK1,
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schedule1, schedule2, vW2, vW3, vW4, vW5, vW6, vW7, vW0, vW1)
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do_round2(v3, v0, v4, v2, v1,
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load_k_3, vK2,
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schedule1, schedule2, vW3, vW4, vW5, vW6, vW7, vW0, vW1, vW2)
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do_round2(v2, v3, v1, v4, v0,
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_, vK0,
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schedule1, schedule2, vW4, vW5, vW6, vW7, vW0, vW1, vW2, vW3)
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do_round2(v4, v2, v0, v1, v3,
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_, vK1,
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schedule1, schedule2, vW5, vW6, vW7, vW0, vW1, vW2, vW3, vW4)
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do_round2(v1, v4, v3, v0, v2,
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load_k_3, vK2,
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schedule1, schedule2, vW6, vW7, vW0, vW1, vW2, vW3, vW4, vW5)
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do_round2(v0, v1, v2, v3, v4,
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_, vK0,
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schedule1, schedule2, vW7, vW0, vW1, vW2, vW3, vW4, vW5, vW6)
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# rounds 33-48
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do_round2(v3, v0, v4, v2, v1,
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_, vK1,
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schedule1, schedule2, vW0, vW1, vW2, vW3, vW4, vW5, vW6, vW7)
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do_round2(v2, v3, v1, v4, v0,
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load_k_3, vK2,
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schedule1, schedule2, vW1, vW2, vW3, vW4, vW5, vW6, vW7, vW0)
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do_round2(v4, v2, v0, v1, v3,
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_, vK0,
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schedule1, schedule2, vW2, vW3, vW4, vW5, vW6, vW7, vW0, vW1)
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do_round2(v1, v4, v3, v0, v2,
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_, vK1,
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schedule1, schedule2, vW3, vW4, vW5, vW6, vW7, vW0, vW1, vW2)
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do_round2(v0, v1, v2, v3, v4,
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load_k_3, vK2,
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schedule1, schedule2, vW4, vW5, vW6, vW7, vW0, vW1, vW2, vW3)
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do_round2(v3, v0, v4, v2, v1,
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_, vK0,
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schedule1, schedule2, vW5, vW6, vW7, vW0, vW1, vW2, vW3, vW4)
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do_round2(v2, v3, v1, v4, v0,
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_, vK1,
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schedule1, schedule2, vW6, vW7, vW0, vW1, vW2, vW3, vW4, vW5)
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do_round2(v4, v2, v0, v1, v3,
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load_k_3, vK2,
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schedule1, schedule2, vW7, vW0, vW1, vW2, vW3, vW4, vW5, vW6)
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# rounds 49-64
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do_round2(v1, v4, v3, v0, v2,
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_, vK0,
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schedule1, schedule2, vW0, vW1, vW2, vW3, vW4, vW5, vW6, vW7)
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do_round2(v0, v1, v2, v3, v4,
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_, vK1,
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schedule1, schedule2, vW1, vW2, vW3, vW4, vW5, vW6, vW7, vW0)
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do_round2(v3, v0, v4, v2, v1,
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load_k_3, vK2,
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schedule1, schedule2, vW2, vW3, vW4, vW5, vW6, vW7, vW0, vW1)
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do_round2(v2, v3, v1, v4, v0,
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_, vK0,
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schedule1, schedule2, vW3, vW4, vW5, vW6, vW7, vW0, vW1, vW2)
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do_round2(v4, v2, v0, v1, v3,
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_, vK1,
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schedule1, schedule2, vW4, vW5, vW6, vW7, vW0, vW1, vW2, vW3)
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do_round2(v1, v4, v3, v0, v2,
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load_k_3, vK2,
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schedule1, schedule2, vW5, vW6, vW7, vW0, vW1, vW2, vW3, vW4)
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do_round2(v0, v1, v2, v3, v4,
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_, vK0,
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schedule1, schedule2, vW6, vW7, vW0, vW1, vW2, vW3, vW4, vW5)
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do_round2(v3, v0, v4, v2, v1,
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_, vK1,
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schedule1, schedule2, vW7, vW0, vW1, vW2, vW3, vW4, vW5, vW6)
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cbz x2, .Lend
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# rounds 65-80
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do_round2(v2, v3, v1, v4, v0,
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load_k_3, vK2,
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_, _, vW0, , , , , , , )
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do_round2(v4, v2, v0, v1, v3,
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_, vK0,
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_, _, vW1, , , , , , , )
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do_round2(v1, v4, v3, v0, v2,
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_, vK1,
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_, _, vW2, , , , , , , )
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do_round2(v0, v1, v2, v3, v4,
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load_k_3, vK2,
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_, _, vW3, , , , , , , )
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do_round2(v3, v0, v4, v2, v1,
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_, vK0,
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load_msg1, _, vW4, , , , , , , )
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do_round2(v2, v3, v1, v4, v0,
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_, vK1,
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load_msg2, _, vW5, , , , , , , )
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do_round2(v4, v2, v0, v1, v3,
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load_k_last, vK2,
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load_msg3, _, vW6, , , , , , , )
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mov x3, x4
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do_round2(v1, v4, v3, v0, v2,
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load_k_3, vK0,
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load_msg4, load_msg5, vW7, , , , , , , )
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load_msg6()
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load_msg7()
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add vH01.2d, vH01.2d, v0.2d
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add vH23.2d, vH23.2d, v1.2d
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add vH45.2d, vH45.2d, v2.2d
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add vH67.2d, vH67.2d, v3.2d
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load_msg8()
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load_msg9()
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load_msg10()
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mov v0.16b, vH01.16b
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mov v1.16b, vH23.16b
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mov v2.16b, vH45.16b
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mov v3.16b, vH67.16b
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b .Loop
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.Lend:
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# rounds 65-80
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do_round2(v2, v3, v1, v4, v0,
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load_k_3, vK2,
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CLEAR_REG, _, vW0, , , , , , , )
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do_round2(v4, v2, v0, v1, v3,
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_, vK0,
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CLEAR_REG, _, vW1, , , , , , , )
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do_round2(v1, v4, v3, v0, v2,
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_, vK1,
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CLEAR_REG, _, vW2, , , , , , , )
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do_round2(v0, v1, v2, v3, v4,
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load_k_3, vK2,
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CLEAR_REG, _, vW3, , , , , , , )
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do_round2(v3, v0, v4, v2, v1,
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_, vK0,
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CLEAR_REG, _, vW4, , , , , , , )
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do_round2(v2, v3, v1, v4, v0,
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_, vK1,
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CLEAR_REG, _, vW5, , , , , , , )
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CLEAR_REG(vK1)
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do_round2(v4, v2, v0, v1, v3,
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load_k_last, vK2,
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CLEAR_REG, _, vW6, , , , , , , )
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CLEAR_REG(vK2)
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do_round2(v1, v4, v3, v0, v2,
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_, vK0,
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CLEAR_REG, _, vW7, , , , , , , )
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CLEAR_REG(vK0)
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CLEAR_REG(v4)
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add vH01.2d, vH01.2d, v0.2d
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CLEAR_REG(v0)
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add vH23.2d, vH23.2d, v1.2d
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CLEAR_REG(v1)
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add vH45.2d, vH45.2d, v2.2d
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CLEAR_REG(v2)
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add vH67.2d, vH67.2d, v3.2d
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CLEAR_REG(v3)
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CLEAR_REG(vT0)
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CLEAR_REG(vT1)
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CLEAR_REG(vT2)
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CLEAR_REG(vT3)
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|
||||
st1 {vH01.2d-vH67.2d}, [x0] /* store state */
|
||||
|
||||
CLEAR_REG(vH01)
|
||||
CLEAR_REG(vH23)
|
||||
CLEAR_REG(vH45)
|
||||
CLEAR_REG(vH67)
|
||||
|
||||
.Ldo_nothing:
|
||||
mov x0, #0
|
||||
ret_spec_stop
|
||||
CFI_ENDPROC()
|
||||
ELF(.size _gcry_sha512_transform_armv8_ce,.-_gcry_sha512_transform_armv8_ce;)
|
||||
|
||||
#endif
|
||||
Reference in new issue
Block a user